The present invention relates to an output pulse generating apparatus for generating and outputting an output pulse having an arbitrary waveform in accordance with a command supplied from a CPU (central processing unit).
An output pulse generating apparatus can generate an output pulse base on data for designating an output value of a pulse to be generated and data for designating an output timing of the output value, both of which are sent from a CPU. An apparatus capable of generating such an output pulse is combined with an actuator and used for controlling various apparatuses. For example, an output pulse generating apparatus used for automobile engine control is disclosed in Japanese Patent Publication No. 60-2510. This apparatus will be described with reference to FIG. 1.
Referring to FIG. 1, a CPU (not shown) sets time points TA, TB, TC, and TD of state changes (changes in output value) of respective output pulses A, B, C, and D (refer to FIG. 2) in corresponding registers 101, 102, 103, and 104. The CPU also sets output values DA, DB, DC, and DD at the respective state change time points in registers 105, 106, 107, and 108. A reference time point signal designating a reference time point generated by timer counter 109, and time points TA to TD stored in registers 101 and 104 are time-divisionally switched by change over switch 110 and compared with each other in comparator 111. This comparison result is time-divisionally switched by change over switch 112 and sequentially supplied to the G terminals of D-type flip-flops 113, 114, 115, and 116. Output values DA to DD are latched by flip-flops 113 to 116 in accordance with the comparison result, and output pulses A, B, C and D are generated.
When 4 output values A, B, C, and D in FIG. 2 are obtained using the pulse generating apparatus in FIG. 1, the CPU (not shown) performs processing in FIG. 3.
More specifically, after the CPU sets output values DA to DD and time points TA to TD in registers 101 to 108, the CPU performs other operations until an interruption is generated in response to a coincidence output from comparator 111. When the interruption is generated, the CPU sets the next values in corresponding registers. In FIG., .circle.1 to .circle.13 to indicate the respective processing sections divided by interruptions to the CPU. By performing the above processing, the CPU can perform other operations for a time other than the time from when the CPU receives an interruption to when time point data TA to TD and output data DA to DD are updated.
The conventional apparatus in FIG. 1 poses the following drawbacks. Since comparison and latch operations are time-divisionally performed in each channel (one pulse corresponding to one channel), even if the set time points of the output timing of output values A to D coincide with each other as indicated by a broken line in FIG. 4A, in practice, the time points of output pulses A, B, C, and D are successively shifted by ts. In this case, ts indicates a time interval required for the switching operation of change over switches 110 and 112. For this reason, precision in pulse output time point is degraded.
Since only a pulse state change at a given time point can be controlled between interruptions to the CPU at the first and second time points, the leading and trailing edges must be set for each pulse even in the case of periodic pulses. Therefore, a load on the CPU is increased. In addition, since a minimum time interval between state changes in output pulse is influenced by operation clocks, a narrow-width pulse or a high-speed pulse cannot be produced.